Test planning for core-based system-on-a-chip (SOC) designs necessary to reduce testing time and test cost. In this paper, we sur-vey recent advances in test planning that address the problems of access and constrained test scheduling for core-based SOCs. We describe several test access architectures proposed by research groups in industry and academia, as well as a wide range of methodologies for the optimization of such architectures. An extensive list of references to prior and current work in the SOC test planning domain included.