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Vector Memory Expansion System For T33xx Logic Tester
Guam, USA November 18-November 20
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2002.118174311th Asian Test Symposium (ATS'02)
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Kazuhiro Yamada, Yoshikazu Takahashi, "Vector Memory Expansion System For T33xx Logic Tester," Asian Test Symposium, pp. 392, 11th Asian Test Symposium (ATS'02), 2002.
 
 
BibTex
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@article{ 10.1109/ATS.2002.1181743,
author = {Kazuhiro Yamada and Yoshikazu Takahashi},
title = {Vector Memory Expansion System For T33xx Logic Tester},
journal ={Asian Test Symposium},
volume = {0},
year = {2002},
issn = {1081-7735},
pages = {392},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2002.1181743},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Asian Test Symposium
TI - Vector Memory Expansion System For T33xx Logic Tester
SN - 1081-7735
SP
EP
A1 - Kazuhiro Yamada,
A1 - Yoshikazu Takahashi,
PY - 2002
KW - null
VL - 0
JA - Asian Test Symposium
ER -
 
Kazuhiro Yamada, IBM Japan, Ltd.
Yoshikazu Takahashi, IBM Japan, Ltd.
This paper describes a low-cost memory expansion system for the Advantest T33XX logic tester series. Using this system, the T33XX tester has the same capability as the T6672 tester. This system will allow the T33XX to be used for ASIC wafer testing until 2010.
Keywords: T33XX LSSD vector pattern DFT
Citation:
Kazuhiro Yamada, Yoshikazu Takahashi, "Vector Memory Expansion System For T33xx Logic Tester," ats, pp.392, 11th Asian Test Symposium (ATS'02), 2002
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