In this paper, test time reduction for I _DDQ testing is discussed. Although I _DDQ testing is known to be effective to detect faults in CMOS circuit, test time of I_DDQ testing is larger than that of logic testing. It is shown that test time of I _DDQ test mostly depends on switching current. To reduce test time of I _DDQ testing, the procedure to arrange test vectors such that switching current quickly disappears is proposed for combinational circuits. The procedure utilizes a unit delay model to estimate the time of the last transition of logic value from L to H in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure.