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Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning
Xi?an, China November 16-November 19
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2003.125077412th Asian Test Symposium (ATS'03)
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Dong Xiang, Tsinghua University
Ming-Jing Chen, Tsinghua University
Jia-Guang Sun, Tsinghua University
Hideo Fujiwara, Nara Institute of Science and Technology
Test effectiveness of a test-per-scan BIST scheme is highly dependent on the length and the number of the scan chains. Fewer cycles are adopted to capture test responses when the length of the scan chains increases. On the other hand, the number of test inputs should be increased when the number of the scan chains increases. Another important feature of the test-per-scan BIST scheme is that test responses of the circuit at the inputs of the scan flip-flops are unobservable during the shift cycles. A new scan architecture is proposed to make a scan-based circuit more observable. The scan chain is partitioned into multiple segments, according to which multiple capture cycles can be inserted to receive test responses during the shift cycles based on the test-per-scan test scheme. This scheme directly makes the circuit more observable and testable. Unlike other BIST schemes using multiple capture cycles after the shift cycles, our method inserts multiple capture cycles inside the shift cycles, but not after the shift cylces. Sufficient experimental results are presented to demonstrate the effectiveness of the method.
Citation:
Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara, "Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning," ats, pp.12, 12th Asian Test Symposium (ATS'03), 2003
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