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PLL Based High Speed Functional Testing
Xi?an, China November 16-November 19
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2003.125079412th Asian Test Symposium (ATS'03)
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Jayasanker Jayabalan, National University of Singapore
Chee Kiang Goh, Infineon Technologies
Ooi Ban Leong, National University of Singapore
Leong Mook Seng, National University of Singapore
Mahadevan K. Iyer, Institute of Microelectronics
Andrew A.O. Tay, National University of Singapore
A PLL based at-speed functional testing concept, which eliminates the need for a tester-driven high-speed clock interface is presented. Jitter tolerance circuits have been implemented to provide immunity to clock jitter. The concept was verified on a 100 square mm silicon device built in 0.18 micron technology above 200 MHz speed. Simulation results show that the concept can be extended to higher speeds.
Citation:
Jayasanker Jayabalan, Chee Kiang Goh, Ooi Ban Leong, Leong Mook Seng, Mahadevan K. Iyer, Andrew A.O. Tay, "PLL Based High Speed Functional Testing," ats, pp.116, 12th Asian Test Symposium (ATS'03), 2003
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