Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing

Xi?an, China November 16-November 19

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http://doi.ieeecomputersociety.org/10.1109/ATS.2003.1250835

12th Asian Test Symposium (ATS'03)

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	Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, Andr? Ivanov, "Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing," Asian Test Symposium, pp. 348, 12th Asian Test Symposium (ATS'03), 2003.

	BibTex	x
	@article{ 10.1109/ATS.2003.1250835, author = {Baosheng Wang and Yong B. Cho and Sassan Tabatabaei and Andr? Ivanov}, title = {Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing}, journal ={Asian Test Symposium}, volume = {0}, year = {2003}, issn = {1081-7735}, pages = {348}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2003.1250835}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing SN - 1081-7735 SP EP A1 - Baosheng Wang, A1 - Yong B. Cho, A1 - Sassan Tabatabaei, A1 - Andr? Ivanov, PY - 2003 KW - Timing specifications testing KW - Test Environment KW - Yield analysis KW - Tester OTA and yield KW - High-speed interconnect testing VL - 0 JA - Asian Test Symposium ER -

Baosheng Wang, University of British Columbia

Yong B. Cho, Konkuk University

Sassan Tabatabaei, Vector 12 Corporation

Andr? Ivanov, University of British Columbia

This paper extends the model in [4] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures? impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a defect level of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter.

Index Terms:

Timing specifications testing, Test Environment, Yield analysis, Tester OTA and yield, High-speed interconnect testing

Citation:

Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, Andr? Ivanov, "Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing," ats, pp.348, 12th Asian Test Symposium (ATS'03), 2003

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