loading...
Test Power Reduction with Multiple Capture Orders
Kenting, Taiwan November 15-November 17
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2004.8213th Asian Test Symposium (ATS'04)
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Kuen-Jong Lee, National Cheng Kung University
Shaing-Jer Hsu, National Cheng Kung University
Chia-Ming Ho, National Cheng Kung University
This paper proposes a novel method to reduce the excess power dissipation during scan testing. The proposed method divides a scan chain into a number of sub-chains, and enables only one sub-chain at a time for both the scan and capture operations. To efficiently deal with the data dependence problem during the capture cycles, we develop a multiple-capture-orders method to guarantee the full scan fault coverage. A novel test pattern generation procedure is developed to reduce the test application time and a test architecture based on a ring control structure is adopted which makes the test control very simple and requires very low area overhead. Experimental results for large ISCAS?89 benchmark circuits show that the proposed method can reduce average and peak power by 86.8% and 66.1% in average, respectively, when 8 sub-chains are used.
Citation:
Kuen-Jong Lee, Shaing-Jer Hsu, Chia-Ming Ho, "Test Power Reduction with Multiple Capture Orders," ats, pp.26-31, 13th Asian Test Symposium (ATS'04), 2004
Usage of this product signifies your acceptance of the Terms of Use.