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Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity
Kenting, Taiwan November 15-November 17
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2004.5713th Asian Test Symposium (ATS'04)
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Debesh Kumar Das, Jadavpur University
Tomoo Inoue, Hiroshima City University
Susanta Chakraborty, Kalyani University
Hideo Fujiwara, Nara Institute of Science and Technology
The paper uses the concept of time expansion model [9] to find the test generation for acyclic sequential circuits. It identifies a class of sequential circuits called as max-testable sequential circuits, where test generation can be obtained using a combinational test generator with the capability of detecting multiple faults on a kernel of combinational circuit. Any acyclic sequential circuit without hold registers belongs to this class. For the sequential circuits having hold registers, a subset of such circuits are found to be belonged to max-testable class. The paper also suggests an algorithm to find such class of circuits.
Citation:
Debesh Kumar Das, Tomoo Inoue, Susanta Chakraborty, Hideo Fujiwara, "Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity," ats, pp.342-347, 13th Asian Test Symposium (ATS'04), 2004
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