This paper presents a new method for the testing of the datapath of DSP cores based on self-test program. During the test, random patterns are loaded into the core, exercise different components of the core, and then are loaded out of the core for observation under the control of the self-test programs. We propose a systematic approach to generate the self-test program based on two metrics. One is the structural coverage and the other is the testability metric. Experimental results show the self-test program obtained by this approach can reach very high fault coverage in programmable core testing. A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits83590292abs.htm Manfred Koegst, Dieter Garte Fraunhofer-Institut f?r Integrierte Schaltungen, EAS DresdenPeter Conradi, , Michael WahlUniversit?t-GH SiegenIn this paper a number of reuse approaches for circuit design are analysed. Based on this analysis an algebraic core model for discussion of a general reuse strategy is proposed. Using this model, the aim is to classify different reuse approaches for circuit design, to compare the applied terms and definitions, and to formulate classes of typical reuse tasks. In a practical application with focus on retrieval and parameterisation techniques, this model is on the way to being applied to DSP design issues. Reconfigurable Logic for Systems on a Chip83590340abs.htm W. Shields NeelyNational SemiconductorThe electronic systems of the future will be implemented in terms of multi-million gate "systems on a chip". These systems will require an enormous investment in design and manufacturing; yet the pace of technological change (e.g., new algorithm development, new processor and memory designs) and ever changing requirements puts them in danger of obsolescence soon after they are created - applications always want to take advantage of new technical advances and must meet changed requirements. What is needed are single chip systems that are designed to be adaptable to a family of applications. The emerging technology of configurable logic offers the promise of large-scale silicon systems that are adaptive after manufacture, with little or no sacrifice in execution efficiency compared to hard-wired systems.