On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits

Paris, France February 23-February 26

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655923

Design Automation and Test in Europe ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Lluis Ribas Articles by Jordi Carrabina

	ASCII Text	x
	Lluis Ribas, Jordi Carrabina, "On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits," Design, Automation and Test in Europe Conference and Exhibition, pp. 624, Design Automation and Test in Europe (DATE '98), 1998.

	BibTex	x
	@article{ 10.1109/DATE.1998.655923, author = {Lluis Ribas and Jordi Carrabina}, title = {On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {1998}, isbn = {0-8186-8359-7}, pages = {624}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655923}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits SN - 0-8186-8359-7 SP EP A1 - Lluis Ribas, A1 - Jordi Carrabina, PY - 1998 KW - incremental simulation KW - switch-level circuit analysis KW - symbolic circuit traversal VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Lluis Ribas, Autonomous University of Barcelona (UAB)

Jordi Carrabina, Autonomous University of Barcelona (UAB)

Incremental methods are successfully applied to deal with successive verifications of slightly modified switch-level networks. That is, only those parts affected by the changes are symbolically traversed for verification. In this paper, we present an incremental technique for symbolic simulators which is inspired in both existing incremental techniques for non-symbolic simulators and a token-passing mechanisms in Petri nets.

Index Terms:

incremental simulation, switch-level circuit analysis, symbolic circuit traversal

Citation:

Lluis Ribas, Jordi Carrabina, "On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits," date, pp.624, Design Automation and Test in Europe (DATE '98), 1998

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.