Automatic Verification of Scheduling Results in High-Level Synthesis

Munich, Germany March 09-March 12

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http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761097

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	ASCII Text	x
	Hans Eveking, Holger Hinrichsen, Gerd Ritter, "Automatic Verification of Scheduling Results in High-Level Synthesis," Design, Automation and Test in Europe Conference and Exhibition, pp. 59, Design, Automation and Test in Europe (DATE '99), 1999.

	BibTex	x
	@article{ 10.1109/DATE.1999.761097, author = {Hans Eveking and Holger Hinrichsen and Gerd Ritter}, title = {Automatic Verification of Scheduling Results in High-Level Synthesis}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {1999}, issn = {1530-1591}, pages = {59}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761097}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Automatic Verification of Scheduling Results in High-Level Synthesis SN - 1530-1591 SP EP A1 - Hans Eveking, A1 - Holger Hinrichsen, A1 - Gerd Ritter, PY - 1999 VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

Hans Eveking, Darmstadt University of Technology

Holger Hinrichsen, Darmstadt University of Technology

Gerd Ritter, Darmstadt University of Technology

A method for the fully automatic equivalence verification of a design before and after the scheduling step of high-level synthesis is presented. The technique is applicable to the results of advanced scheduling methods like AFAP and DLS, which work on cyclic control flows, as well as to pipelined designs.

Citation:

Hans Eveking, Holger Hinrichsen, Gerd Ritter, "Automatic Verification of Scheduling Results in High-Level Synthesis," date, pp.59, Design, Automation and Test in Europe (DATE '99), 1999

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