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Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits
Munich, Germany March 09-March 12
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761115Design, Automation and Test in Europe ...
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Michael S. Hsiao, "Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits," Design, Automation and Test in Europe Conference and Exhibition, pp. 175, Design, Automation and Test in Europe (DATE '99), 1999.
 
 
BibTex
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@article{ 10.1109/DATE.1999.761115,
author = {Michael S. Hsiao},
title = {Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {0},
year = {1999},
issn = {1530-1591},
pages = {175},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761115},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits
SN - 1530-1591
SP
EP
A1 - Michael S. Hsiao,
PY - 1999
VL - 0
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Michael S. Hsiao, Rutgers University
Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP) of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times.
Citation:
Michael S. Hsiao, "Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits," date, pp.175, Design, Automation and Test in Europe (DATE '99), 1999
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