Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach

Munich, Germany March 09-March 12

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http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761166

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	ASCII Text	x
	M. Bühler, M. Papesch, K. Kapp, U.G. Baitinger, "Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach," Design, Automation and Test in Europe Conference and Exhibition, pp. 459, Design, Automation and Test in Europe (DATE '99), 1999.

	BibTex	x
	@article{ 10.1109/DATE.1999.761166, author = {M. Bühler and M. Papesch and K. Kapp and U.G. Baitinger}, title = {Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {1999}, issn = {1530-1591}, pages = {459}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761166}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach SN - 1530-1591 SP EP A1 - M. Bühler, A1 - M. Papesch, A1 - K. Kapp, A1 - U.G. Baitinger, PY - 1999 VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

M. Bühler, University of Stuttgart

M. Papesch, University of Stuttgart

K. Kapp, University of Stuttgart

U.G. Baitinger, University of Stuttgart

Estimating switching activity is a crucial step in optimiz ing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits will be presented. The combination of event driven and bitparallel simulation allows for high accuracy due to the real delay model of the former while maintaining the speedup of the latter. This is demonstrated by detailed experimental results.

Citation:

M. Bühler, M. Papesch, K. Kapp, U.G. Baitinger, "Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach," date, pp.459, Design, Automation and Test in Europe (DATE '99), 1999

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