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Digital MOS Circuit Partitioning with Symbolic Modeling
Munich, Germany March 09-March 12
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761173Design, Automation and Test in Europe ...
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Lluis Ribas, Jordi Carrabina, "Digital MOS Circuit Partitioning with Symbolic Modeling," Design, Automation and Test in Europe Conference and Exhibition, pp. 503, Design, Automation and Test in Europe (DATE '99), 1999.
 
 
BibTex
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@article{ 10.1109/DATE.1999.761173,
author = {Lluis Ribas and Jordi Carrabina},
title = {Digital MOS Circuit Partitioning with Symbolic Modeling},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {0},
year = {1999},
issn = {1530-1591},
pages = {503},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761173},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - Digital MOS Circuit Partitioning with Symbolic Modeling
SN - 1530-1591
SP
EP
A1 - Lluis Ribas,
A1 - Jordi Carrabina,
PY - 1999
KW - circuit partitioning
KW - switch-level circuit analysis
KW - symbolic circuit traversal
KW - symbolic modeling
VL - 0
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
Lluis Ribas, Autonomous University of Barcelona (UAB)
Jordi Carrabina, Autonomous University of Barcelona (UAB)
This paper presents a method to automatically recognize and model single and multi-output logic gates out of a switch-level network, even for irregular transistor structures. Result subcircuit models are directly used in a symbolic simulator for circuit analysis purposes. Other applications of derived netlists cover switch-level simulation acceleration and test generation tool enhancement.
Index Terms:
circuit partitioning, switch-level circuit analysis, symbolic circuit traversal, symbolic modeling
Citation:
Lluis Ribas, Jordi Carrabina, "Digital MOS Circuit Partitioning with Symbolic Modeling," date, pp.503, Design, Automation and Test in Europe (DATE '99), 1999
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