High Speed GaAs Subsystem Design using Feed Through Logic

Munich, Germany March 09-March 12

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http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761174

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	ASCII Text	x
	J. A. Montiel-Nelson, S. Nooshabadi, V. de Armas, R. Sarmiento, A. Nunez, "High Speed GaAs Subsystem Design using Feed Through Logic," Design, Automation and Test in Europe Conference and Exhibition, pp. 509, Design, Automation and Test in Europe (DATE '99), 1999.

	BibTex	x
	@article{ 10.1109/DATE.1999.761174, author = {J. A. Montiel-Nelson and S. Nooshabadi and V. de Armas and R. Sarmiento and A. Nunez}, title = {High Speed GaAs Subsystem Design using Feed Through Logic}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {1999}, issn = {1530-1591}, pages = {509}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1999.761174}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - High Speed GaAs Subsystem Design using Feed Through Logic SN - 1530-1591 SP EP A1 - J. A. Montiel-Nelson, A1 - S. Nooshabadi, A1 - V. de Armas, A1 - R. Sarmiento, A1 - A. Nunez, PY - 1999 KW - GaAs fast arithmetic circuits KW - GaAs design methodologies KW - GaAs subsystem design KW - GaAs ripple-carry adders KW - GaAs magnitude comparators. VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

J. A. Montiel-Nelson, University of Las Palmas de Gran Canaria

S. Nooshabadi, University of Las Palmas de Gran Canaria

V. de Armas, University of Las Palmas de Gran Canaria

R. Sarmiento, University of Las Palmas de Gran Canaria

A. Nunez, University of Las Palmas de Gran Canaria

In this paper design of fast arithmetic circuits using GaAs based Feed Through Logic (FTL) family is presented. A modified version of FTL termed Differential FTL (DFTL) is introduced and basic aspects of design methologies using FTL are discussed. A 4-bit ripple-carry adder is designed and its performance is evaluated against other similar reported works in terms of, device count, chip area, delay, clock rate, and power consumption. It is shown how arithmetic circuits based on FTL outperform the evaluated performance. A 4-bit magnitude comparator is designed and performance evaluated against four cascaded 1-bit comparators.

Index Terms:

GaAs fast arithmetic circuits, GaAs design methodologies, GaAs subsystem design, GaAs ripple-carry adders, GaAs magnitude comparators.

Citation:

J. A. Montiel-Nelson, S. Nooshabadi, V. de Armas, R. Sarmiento, A. Nunez, "High Speed GaAs Subsystem Design using Feed Through Logic," date, pp.509, Design, Automation and Test in Europe (DATE '99), 1999

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