Retiming is an efficient technique for redistributing registers in synchronous circuits in order to improve the circuit performance. However, the traditional retiming approaches cannot handle circuits whose registers are controlled by different clock, reset, and load enable signals. We present basic theory and a comprehensive retiming approach for circuits with multiple clock, reset, and load enable signals. We retime these circuits having multiple register classes without explicitly modeling the reset or the load enable by additional logic. The presented concepts can be combined with a wide range of existing retiming approaches. Experimental results from retiming real designs for clock period minimization show the efficiency of the new approach.