A Hardware Platform for VLIW Based Emulation of Digital Designs

Paris, France March 27-March 30

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http://doi.ieeecomputersociety.org/10.1109/DATE.2000.840880

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	ASCII Text	x
	G. Haug, U. Kebschull, W. Rosenstiel, "A Hardware Platform for VLIW Based Emulation of Digital Designs," Design, Automation and Test in Europe Conference and Exhibition, pp. 747, Design, Automation and Test in Europe (DATE '00), 2000.

	BibTex	x
	@article{ 10.1109/DATE.2000.840880, author = {G. Haug and U. Kebschull and W. Rosenstiel}, title = {A Hardware Platform for VLIW Based Emulation of Digital Designs}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {0}, year = {2000}, issn = {1530-1591}, pages = {747}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2000.840880}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - A Hardware Platform for VLIW Based Emulation of Digital Designs SN - 1530-1591 SP EP A1 - G. Haug, A1 - U. Kebschull, A1 - W. Rosenstiel, PY - 2000 VL - 0 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

G. Haug

U. Kebschull

W. Rosenstiel

In this paper an the concept of a very long instruction word (VLIW) processor based system to emulate synthesized RT-level descriptions is descibed. The RAVE System (RT Architecture VLIW Emulator) overcomes many of the problems common to FPGA based emulation and prototyping systems. Particularly, these are area problems in conjunction with large data paths, long turnaround times and low emulation clock frequencies. This abstract briefly describes the hardware of the RAVE System.

Citation:

G. Haug, U. Kebschull, W. Rosenstiel, "A Hardware Platform for VLIW Based Emulation of Digital Designs," date, pp.747, Design, Automation and Test in Europe (DATE '00), 2000

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