loading...
Gate Level Fault Diagnosis in Scan-Based BIST
Paris, France March 04-March 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2002.9983012002 Design, Automation and Test in E ...
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test vector information and enables location identification of single stuck-at faults to a neighborhood of a few gates through set operations on small pass/fail dictionaries. The proposed scheme is applicable to multiple stuck-at faults and bridging faults as well. The practical applicability of the suggested ideas is confirmed through numerous experimental runs on all three fault models.
Citation:
I. Bayraktaroglu, A. Orailoglu, "Gate Level Fault Diagnosis in Scan-Based BIST," date, pp.0376, 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02), 2002
Usage of this product signifies your acceptance of the Terms of Use.