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False Path Elimination in Quasi-Static Scheduling
Paris, France March 04-March 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2002.9984162002 Design, Automation and Test in E ...
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We have developed a technique to compute a Quasi Static Schedule of a concurrent specification for the software partition of an embedded system. Previous work did not take into account correlations among run-time values of variables, and therefore tried to find a schedule for all possible outcomes of conditional expressions. This is advantageous on one hand, because by abstracting data values one can find schedules in many cases for an originally undecidable problem. On the other hand it may lead to exploring false paths, i.e., paths that can never happen at run-time due to constraints on how the variables are updated. This affects the applicability of the approach, because it leads to an explosion in the running time and the memory requirements of the compile-time scheduler itself. Even worse, it also leads to an increase in the final code size of the generated software.
In this paper, we propose a semi-automatic algorithm to solve the problem of false paths: the designer identifies and tags critical expressions, and synchronization channels are automatically added to the specification to drive the search of a schedule. As a proof of concept, the proposed technique has been applied to a subsystem of an MPEG-2 decoder, and allowed us to find a schedule that previous techniques could not identify.
Citation:
G. Arrigoni, L. Duchini, C. Passerone, L. Lavagno, Y. Watanabe, "False Path Elimination in Quasi-Static Scheduling," date, pp.0964, 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02), 2002
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