SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance

Paris, France February 16-February 20

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http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268942

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	James Chin, Mehrdad Nourani, "SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 10710, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004.

	BibTex	x
	@article{ 10.1109/DATE.2004.1268942, author = {James Chin and Mehrdad Nourani}, title = {SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance}, journal ={Design, Automation and Test in Europe Conference and Exhibition}, volume = {1}, year = {2004}, issn = {1530-1591}, pages = {10710}, doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268942}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Design, Automation and Test in Europe Conference and Exhibition TI - SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance SN - 1530-1591 SP EP A1 - James Chin, A1 - Mehrdad Nourani, PY - 2004 KW - null VL - 1 JA - Design, Automation and Test in Europe Conference and Exhibition ER -

James Chin, University of Texas at Dallas

Mehrdad Nourani, University of Texas at Dallas

We present a test scheduling methodology for core-based system-on-chips that can avoid hot spots and allows tradeoff between physical power dissipation and overall test time. A mixed integer linear programming formulation is presented to globally perform the power-time tradeoff, satisfy constraints, and produce the SoC test schedule.

Citation:

James Chin, Mehrdad Nourani, "SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance," date, vol. 1, pp.10710, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004

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