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Are Our Design for Testability Features Fault Secure?
Paris, France February 16-February 20
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268944Design, Automation and Test in Europe ...
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C. Metra, T.M. Mak, M. Oma?, "Are Our Design for Testability Features Fault Secure?," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 10714, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004.
 
 
BibTex
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@article{ 10.1109/DATE.2004.1268944,
author = {C. Metra and T.M. Mak and M. Oma?},
title = {Are Our Design for Testability Features Fault Secure?},
journal ={Design, Automation and Test in Europe Conference and Exhibition},
volume = {1},
year = {2004},
issn = {1530-1591},
pages = {10714},
doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268944},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Design, Automation and Test in Europe Conference and Exhibition
TI - Are Our Design for Testability Features Fault Secure?
SN - 1530-1591
SP
EP
A1 - C. Metra,
A1 - T.M. Mak,
A1 - M. Oma?,
PY - 2004
KW - null
VL - 1
JA - Design, Automation and Test in Europe Conference and Exhibition
ER -
 
C. Metra, University of Bologna
T.M. Mak, Intel Corporation
M. Oma?, University of Bologna
We analyze the risks associated with faults affecting some common Design For Testability (DFT) features employed within digital products. We will show that some DFT structures may become useless, with consequent dramatic impact on test effectiveness and product quality. We borrow the Fault Secure property and we will show that it guarantees that no escapes or false acceptance of faulty products may occur because of faults within the DFT structures.
Citation:
C. Metra, T.M. Mak, M. Oma?, "Are Our Design for Testability Features Fault Secure?," date, vol. 1, pp.10714, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004
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