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Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design
Paris, France February 16-February 20
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268946Design, Automation and Test in Europe ...
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Ashish Srivastava, University of Michigan
Dennis Sylvester, University of Michigan
David Blaauw, University of Michigan
We present a sensitivity based algorithm for total power including dynamic and subthreshold leakage power minimization using simultaneous sizing, Vdd and Vth assignment. The proposed algorithm is implemented and tested on a set of combinational benchmark circuits. A comparison with traditional CVS based algorithms demonstrates the advantage of the algorithm including an average power reduction of 37% at primary input activities of 0.1. We also investigate the impact of various low Vdd values on total power savings.
Citation:
Ashish Srivastava, Dennis Sylvester, David Blaauw, "Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design," date, vol. 1, pp.10718, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), 2004
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