The growing need for application class specific but still flexible data processing leads to a demand of new computer architectures. Reorganziation and combination of proven design paradigms are promising ways to reach these goals. The fully reconfigurable self-timed bit-serial and fully interlocked MACT architecture is one of those new architectures. Although MACT does not rely on a central controller, its local synchronization still demands special care is taken. This fact is especially true if routers are added to the architecture. In this paper we present fundamental invariants for the high level synthesis of MACT as well as an extended explanation of the routing elements. We prove the usefulness of the architecture by an example implementation of two convolution filters within one data flow graph.