loading...
Design of Routing-Constrained Low Power Scan Chains
Perth, Australia January 28-January 30
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DELTA.2004.10009Second IEEE International Workshop on ...
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Y. Bonhomme, Universit? de Montpellier II / CNRS
P. Girard, Universit? de Montpellier II / CNRS
L. Guiller, Synopsys, Inc.
C. Landrault, Universit? de Montpellier II / CNRS
S. Pravossoudovitch, Universit? de Montpellier II / CNRS
A. Virazel, Universit? de Montpellier II / CNRS
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. Recently, we proposed a technique based on clustering and reordering of scan cells that allows to design low power scan chains [1]. The main feature of this technique is that power consumption during scan testing is minimized while constraints on scan routing are satisfied. In this paper, we propose a new version of this technique. The clustering process has been modified to allow a better distribution of scan cells in each cluster and hence lead to more important power reductions. Results are provided at the end of the paper to highlight this point and show that scan design constraints (length of scan connections, congestion problems) are still satisfied.
Citation:
Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, A. Virazel, "Design of Routing-Constrained Low Power Scan Chains," delta, pp.287, Second IEEE International Workshop on Electronic Design, Test and Applications, 2004
Usage of this product signifies your acceptance of the Terms of Use.