This paper presents an IEEE 1149.1 based defect and fault tolerant scan chain usable for testing and configuring large area and wafer scale integrated systems. It uses the Triple Modular Redundancy (TMR) approach to tolerate defects on critical portions of IEEE1149.1 circuitry. By a suitable distribution of sensitive circuits, failures on power, clock (TCK) and control signals (TMS and nTRST) can be tolerated. Some implementation issues, such as layout regularity and timing are discussed. The yield analysis shows that a basic IEEE 1149.1 scan chain can be a significant yield detractor, and its impact on yield is much larger than the small fraction of the total area it occupies. By contrast, the proposed fault tolerant scan chain maintains a high yield for realistic chain size.