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Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults
Boston, Massachusetts November 03-November 05
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.125009318th IEEE International Symposium on ...
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T. Feng, Oklahoma State University
Y.B. Kim, Northeastern University
V. Piuri, University of Milan
This paper proposes a new fault model and its modeling and analysis methods in a clockless asynchronous wave pipeline for extensive yield evaluation and assurance. It is highly desirable to have an adequate and speci.c pulse fault rate model for establishing a sound theoretical foundation for clockless wave pipeline design for reliability. The pulse fault model is thoroughly identified as the unique fault specifically in the clockless wave pipeline in comparison with conventional wave and wave delay faults. The pulse fault rate is statistically yet practically modeled, and extensively evaluated with respect to various design parameters, such as yield, fault coverage, defect-level, and request level length. An extensive numerical simulation is conducted to demonstrate the effect of the proposed pulse fault on the yield.
Citation:
T. Feng, Y.B. Kim, V. Piuri, "Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults," dft, pp.34, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003
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