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Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard
Boston, Massachusetts November 03-November 05
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.125010118th IEEE International Symposium on ...
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Guido Bertoni, Politecnico di Milano
Luca Breveglieri, Politecnico di Milano
Israel Koren, University of Massachusetts at Amherst
Paolo Maistri, Politecnico di Milano
Vincenzo Piuri, Università di Milano
Concurrent fault detection for hardware implementations of the Advanced Encryption Standard (AES) may provide protection against random faults, and against an attacker who may maliciously inject faults in order to find the encryption secret key. We have recently developed such a scheme which is based on the parity code. In this paper we prove that the parity-based code detects all odd-order faults and allows the location of the most single transient and permanent faults.
Citation:
Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri, "Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard," dft, pp.105, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003
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