Chip Level Power Supply Partitioning for I<sub>DDQ</sub> Testing Using Built-In Current Sensors

Chip Level Power Supply Partitioning for I_DDQ Testing Using Built-In Current Sensors

Boston, Massachusetts November 03-November 05

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http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.1250105

18th IEEE International Symposium on ...

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	ASCII Text	x
	Abhijit Prasad, D. M. H Walker, "Chip Level Power Supply Partitioning for I<sub>DDQ</sub> Testing Using Built-In Current Sensors," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 140, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003.

	BibTex	x
	@article{ 10.1109/DFTVS.2003.1250105, author = {Abhijit Prasad and D. M. H Walker}, title = {Chip Level Power Supply Partitioning for I<sub>DDQ</sub> Testing Using Built-In Current Sensors}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2003}, issn = {1063-6722}, pages = {140}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.1250105}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - Chip Level Power Supply Partitioning for I<sub>DDQ</sub> Testing Using Built-In Current Sensors SN - 1063-6722 SP EP A1 - Abhijit Prasad, A1 - D. M. H Walker, PY - 2003 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

Abhijit Prasad, Texas A&M University

D. M. H Walker, Texas A&M University

The International Technology Roadmap for Semiconductors projects that I_DDQ levels will rise rapidly with each technology node. In addition, manufacturing variations in the I_DDQ level will be difficult to control. The combination will make it increasingly difficult to distinguish defect-free from defective chips via I_DDQ tests. Built-in current sensors (BICSs) have been proposed to increase test resolution by virtually partitioning the supply mesh, so that each partition has a relatively small defect-free I_DDQ level. In the future such a scheme would require 100,000 or more BICSs and thus the partitioning task needs to be automated. This paper presents a practical methodology to do this power supply partitioning.

Citation:

Abhijit Prasad, D. M. H Walker, "Chip Level Power Supply Partitioning for I_DDQ Testing Using Built-In Current Sensors," dft, pp.140, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003

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