A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems

Boston, Massachusetts November 03-November 05

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http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.1250117

18th IEEE International Symposium on ...

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	P.K. Lala, "A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 235, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003.

	BibTex	x
	@article{ 10.1109/DFTVS.2003.1250117, author = {P.K. Lala}, title = {A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems}, journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on}, volume = {0}, year = {2003}, issn = {1063-6722}, pages = {235}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.1250117}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on TI - A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems SN - 1063-6722 SP EP A1 - P.K. Lala, PY - 2003 KW - null VL - 0 JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on ER -

P.K. Lala, University of Arkansas

This paper proposes a new coding technique for single error correction and double error detection in computer memory systems. The number of 1?s in the parity check matrix for the proposed coding is fewer than all currently available codes for this purpose. This results in simplified encoding and decoding circuitry for error detection and correction.

Citation:

P.K. Lala, "A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems," dft, pp.235, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003

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