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On The Yield of Compiler-Based eSRAMs
Cannes, France October 10-October 13
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2004.4519th IEEE International Symposium on ...
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X. Wang, M. Ottavi, F. Meyer, F. Lombardi, "On The Yield of Compiler-Based eSRAMs," Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on, pp. 11-19, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004.
 
 
BibTex
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@article{ 10.1109/DFT.2004.45,
author = {X. Wang and M. Ottavi and F. Meyer and F. Lombardi},
title = {On The Yield of Compiler-Based eSRAMs},
journal ={Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on},
volume = {0},
year = {2004},
issn = {1550-5774},
pages = {11-19},
doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2004.45},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
TI - On The Yield of Compiler-Based eSRAMs
SN - 1550-5774
SP11
EP19
A1 - X. Wang,
A1 - M. Ottavi,
A1 - F. Meyer,
A1 - F. Lombardi,
PY - 2004
KW - null
VL - 0
JA - Defect and Fault-Tolerance in VLSI Systems, IEEE International Symposium on
ER -
 
X. Wang, IBM Corp, Essex Junction (VT) USA
M. Ottavi, Northeastern University Boston (MA) USA
F. Meyer, Wichita State University Wichita (KS) USA
F. Lombardi, Northeastern University Boston (MA) USA
This paper presents an extensive evaluation of the manufacturing yield of embedded SRAMs (eSRAM) which are designed using a memory compiler. The yield is evaluated by considering the different design constructs (generally referred to as kernels) that are used in defining the memory architecture through a compiler. Architectural considerations such as array size and line (word and bit) organization are analyzed. Compiler-based features of different kernels (such as required for decoding) are also treated in detail. An extensive evaluation of the provided redundancy (row, column and combined) is pursued to characterize its impact on the memory yield. Industrial data is used in the evaluation and an industrial ASIC chip (made of multiple eSRAMs) is also considered as design case.
Citation:
X. Wang, M. Ottavi, F. Meyer, F. Lombardi, "On The Yield of Compiler-Based eSRAMs," dft, pp.11-19, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004
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