As design and test complexities of SoCs ever intensify, the balanced utilization of combined Built-In Self-Test (BIST) and Automated Test Equipment (ATE) testing becomes desirable to meet the required minimum fault-coverage while maintaining acceptable cost overhead. The cost associated with combined BIST/ATE testing of such systems mainly consists of 1) the cost induced by the BIST area overhead and 2) the cost induced by the overall testing time. In general, BIST is significantly faster than ATE, while it can provide only limited fault-coverage and driving higher fault-coverage from BIST means additional area cost overhead. On the other hand, higher fault-coverage can be easily achieved from ATE, but excessive use of ATE results in additional test time. Combined fault-coverage from BIST and ATE plays a significant role, since it can affect the area overhead in BIST and test time in BIST/ATE. This paper is to propose a novel probabilistic method to balance the fault-coverage and the test overhead costs in combined BIST/ATE test environment. The proposed technique is then applied to two BIST/ATE test scenarios to find the optimal fault-coverage/cost combinations.