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Monitoring Methodology for TID Damaging of SDRAM Devices based on Retention Time Analysis
Cannes, France October 10-October 13
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2004.4019th IEEE International Symposium on ...
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S. Bertazzoni, University of Rome "Tor Vergata", Italy
D. Di Giovenale, University of Rome "Tor Vergata", Italy
M. Salmeri, University of Rome "Tor Vergata", Italy
A. Mencattini, University of Rome "Tor Vergata", Italy
A. Salsano, University of Rome "Tor Vergata", Italy
M. Florean, University of Rome "Tor Vergata", Italy
J. Wyss, INFN Sezione di Pisa, Italy
R. Rando, INFN Sezione di Padova, Italy
S. Lora, Istituto per la Sintesi Organica e la Fotoreattivit?, Italy
Total Ionizing Dose (TID) is a potential problem for solid state devices exposed to ionizing radiations. An important parameter to define is the level of TID the device can tolerate. This value is very useful in order to predict its operative life time in a radiation environment. In this paper an online monitoring method to measure the degradation of Synchronous Dynamic RAM (SDRAM) Commercial Off The Shelf (COTS) devices due to TID is proposed. The method is based on the measurement of the bit retention time, that is the time the information is retained in a memory cell without refresh. This approach is based on the observation that on same die, a dispersion of the devices' characteristics exist. So, the device degradation will appear in a more evident way in those memory cells having worst electrical characteristics. For this reason, there is a gradual increment of the number of memory cells that do not maintain their initialization value with the increment of the absorbed dose.
The proposed method is useful to monitor the real level of degradation of a SDRAM device in order to optimize maintenance activity and graceful performance degradation techniques. SDRAM devices are used as a TID radiation detector to monitor the real dose absorbed by itself, and thus by the whole apparatus. The method is based on functional test that a SDRAM controller can easily perform on empty memory blocks without requiring dedicated hardware.
This paper presents the experimental setup and the results of a preliminary TID test with a 60 Co gamma ray source on SDRAM COTS to validate the method.
Citation:
S. Bertazzoni, D. Di Giovenale, M. Salmeri, A. Mencattini, A. Salsano, M. Florean, J. Wyss, R. Rando, S. Lora, "Monitoring Methodology for TID Damaging of SDRAM Devices based on Retention Time Analysis," dft, pp.106-110, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004
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