Reversible logic is of the growing importance to many future technologies. A reversible circuit maps each output vector, into a unique input vector, and vice versa. This paper introduces an approach to synthesis the generalized multi-rail reversible cascades with minimizing the "garbage bit" and number of reversible gates, which is the main challenge of reversible logic synthesis. This proposed full-adder circuit contains only three gates and two garbage outputs whereas earlier full-adder circuit [10,13] requires four gates and produces two garbage outputs and another existing full-adder circuit [6] requires three gates but produces three garbage outputs. Thus, the proposed full-adder circuit is efficient in terms of number of gates with compared to [10,13] as well as in terms of number of garbage outputs with compared to [6].