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Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects
Belek-Antalya, Turkey September 01-September 06
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2003.1231914Euromicro Symposium on Digital System ...
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Gregorio Cappuccino, DEIS - University of Calabria - Rende (CS) - ITALY
The actual operation of a complementary metal-oxide- semiconductor (CMOS) gate driving long resistance - inductance - capacitance (RLC) interconnects is investigated in this paper. Using the alpha-law model, inductance effects of long on-chip interconnects on the operating region of submicron CMOS line-driver transistors are analysed. A computationally efficient closed form expression for the time the MOS transistors of a line driver actually operate in the saturation region is also presented. The accuracy of the novel expression, particularly suitable for CAD tools implementation, is within 15% as compared to SPICE simulations for a wide range of line parameters.
Citation:
Gregorio Cappuccino, "Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects," dsd, pp.138, Euromicro Symposium on Digital Systems Design (DSD'03), 2003
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