A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages

Belek-Antalya, Turkey September 01-September 06

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http://doi.ieeecomputersociety.org/10.1109/DSD.2003.1231915

Euromicro Symposium on Digital System ...

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	ASCII Text	x
	Ling Wang, Henry Selvaraj, "A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages," Digital Systems Design, Euromicro Symposium on, pp. 144, Euromicro Symposium on Digital Systems Design (DSD'03), 2003.

	BibTex	x
	@article{ 10.1109/DSD.2003.1231915, author = {Ling Wang and Henry Selvaraj}, title = {A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages}, journal ={Digital Systems Design, Euromicro Symposium on}, volume = {0}, year = {2003}, isbn = {0-7695-2003-0}, pages = {144}, doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2003.1231915}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Digital Systems Design, Euromicro Symposium on TI - A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages SN - 0-7695-2003-0 SP EP A1 - Ling Wang, A1 - Henry Selvaraj, PY - 2003 KW - null VL - 0 JA - Digital Systems Design, Euromicro Symposium on ER -

Ling Wang, University of Nevada, Las Vegas

Henry Selvaraj, University of Nevada, Las Vegas

In this paper, a scheme is presented to minimize power dissipation through scheduling and partitioning at the behavior level with resources operating at multiple voltages. The scheme uses partitioning to preserve locality in the assignment of operations to hardware units. Experimental results show that the proposed method can efficiently reduce power.

Citation:

Ling Wang, Henry Selvaraj, "A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages," dsd, pp.144, Euromicro Symposium on Digital Systems Design (DSD'03), 2003

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