loading...
Estimating the Utilization of Embedded FPGA Co-Processor
Belek-Antalya, Turkey September 01-September 06
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2003.1231929Euromicro Symposium on Digital System ...
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Yang Qu, VTT Electronics
Juha-Pekka Soininen, VTT Electronics
Embedded FPGA co-processors will bring new alternatives for SoC system designers. Comparison of software implementations and reconfigurable hardware implementations will need fast and easy-to-use estimation techniques. In this paper, we present an estimation approach for the resource utilization of the embedded FPGA co-processor. Our approach is based on the principles of high-level synthesis, such as force-directed scheduling, resource allocation, operation assignment and interconnection binding. The method has been applied to simple test cases and a C-language model of MPEG-2 decoder. The average hardware estimation error of MPEG-2 functions was 25%.
Citation:
Yang Qu, Juha-Pekka Soininen, "Estimating the Utilization of Embedded FPGA Co-Processor," dsd, pp.214, Euromicro Symposium on Digital Systems Design (DSD'03), 2003
Usage of this product signifies your acceptance of the Terms of Use.