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Test scheduling for embedded systems
Belek-Antalya, Turkey September 01-September 06
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2003.1231985Euromicro Symposium on Digital System ...
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Zdenek Kot?sek, Brno University of Technology, Czech Republic
Daniel Mika, Brno University of Technology, Czech Republic
Josef Strnadel, Brno University of Technology, Czech Republic
The paper proposes two approaches to test scheduling. The first one utilizes the concept of TACG (Test Application Conflict Graph). For the testing process the resource utilization model is defined and used for the TACG construction. Different conflicts that must be taken into account during test scheduling are presented. The paper offers a methodology that can be utilized during embedded test design process, the final goal of which is to reduce the overall test application time and power consumption during the test application. The second methodology is based on optimising the test schedule - the test application time, TAM width and power consumption are taken into account during the process. The goal of the methodology is a reasonable trade-off between these parameters.
Citation:
Zdenek Kot?sek, Daniel Mika, Josef Strnadel, "Test scheduling for embedded systems," dsd, pp.463, Euromicro Symposium on Digital Systems Design (DSD'03), 2003
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