In the Digital and Signal Processing (DSP) applications, the main issue in system performance is strongly related to the memory sub-system characteristics and data positions. In such applications, exhaustive data analysis is often highly complex and time consuming whereas the actual bottlenecks are essentially due to the few largest data objects (arrays). Therefore, to ensure a good trade-off between analysis time and efficiency, we focus the optimization on these objects also called 'structures'. Our approach relies on a new graph formalism called 'Data Control Flow Graph' which analyzes an algorithm (written in C), and brings out data structure dependencies while retaining execution order constraints. Manipulating this graph allows to determine an optimized memory mapping according to a fixed memory hierarchy and thus to reduce bus activity, resulting in improved both execution time and energy consumption. This method is also planned to be extended to memory optimization by sizing both the memory hierarchy and the architecture.