A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder

Rennes, France August 31-September 03

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http://doi.ieeecomputersociety.org/10.1109/DSD.2004.1333274

Euromicro Symposium on Digital System ...

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	P. Ciao, G. Colavolpe, L. Fanucci, "A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder," Digital Systems Design, Euromicro Symposium on, pp. 174-181, Euromicro Symposium on Digital System Design (DSD'04), 2004.

	BibTex	x
	@article{ 10.1109/DSD.2004.1333274, author = {P. Ciao and G. Colavolpe and L. Fanucci}, title = {A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder}, journal ={Digital Systems Design, Euromicro Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2203-3}, pages = {174-181}, doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2004.1333274}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Digital Systems Design, Euromicro Symposium on TI - A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder SN - 0-7695-2203-3 SP174 EP181 A1 - P. Ciao, A1 - G. Colavolpe, A1 - L. Fanucci, PY - 2004 KW - null VL - 0 JA - Digital Systems Design, Euromicro Symposium on ER -

P. Ciao, University of Pisa, Italy

G. Colavolpe, University of Parma, Italy

L. Fanucci, IEIIT, National Research Council, Pisa, Italy

This paper presents a 2048 bit, rate ? soft decision decoder for a new class of codes known as Turbo Gallager Codes. The decoder can support up to 1 Gbit/s code rate and performs up to 48 decoding iteration ensuring at the same time high throughput and good coding gain. In order to evaluate the performance and the gate complexity of the decoder VLSI architecture, it has been synthesized in a 0.18 ?m standard-cell CMOS technology.

Citation:

P. Ciao, G. Colavolpe, L. Fanucci, "A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder," dsd, pp.174-181, Euromicro Symposium on Digital System Design (DSD'04), 2004

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