On the Packet-Switched Implementation of a Discrete-Time CNN

Rennes, France August 31-September 03

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http://doi.ieeecomputersociety.org/10.1109/DSD.2004.1333282

Euromicro Symposium on Digital System ...

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	Suleyman Malki, Lambert Spaanenburg, "On the Packet-Switched Implementation of a Discrete-Time CNN," Digital Systems Design, Euromicro Symposium on, pp. 234-241, Euromicro Symposium on Digital System Design (DSD'04), 2004.

	BibTex	x
	@article{ 10.1109/DSD.2004.1333282, author = {Suleyman Malki and Lambert Spaanenburg}, title = {On the Packet-Switched Implementation of a Discrete-Time CNN}, journal ={Digital Systems Design, Euromicro Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2203-3}, pages = {234-241}, doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2004.1333282}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Digital Systems Design, Euromicro Symposium on TI - On the Packet-Switched Implementation of a Discrete-Time CNN SN - 0-7695-2203-3 SP234 EP241 A1 - Suleyman Malki, A1 - Lambert Spaanenburg, PY - 2004 KW - Cellular Neural Network KW - Packet Switching KW - Image Processing KW - FPGA VL - 0 JA - Digital Systems Design, Euromicro Symposium on ER -

Suleyman Malki, Lund University, Sweden

Lambert Spaanenburg, Lund University, Sweden

Cellular Neural Networks are widely used with real-time image processing's applications. Such systems can be efficiently realized using macro enriched field-programmable gate-arrays. This paper explores the benefits of packet switching and discusses its advantages over a current design based on circuit switching. The implementation is performed using Xilinx Virtex-II Pro P30 and handles around 500 Mpixels per second using 128 parallel processing nodes.

Index Terms:

Cellular Neural Network, Packet Switching, Image Processing, FPGA

Citation:

Suleyman Malki, Lambert Spaanenburg, "On the Packet-Switched Implementation of a Discrete-Time CNN," dsd, pp.234-241, Euromicro Symposium on Digital System Design (DSD'04), 2004

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