A Heuristic for Wiring-Aware Built-In Self-Test Synthesis

Rennes, France August 31-September 03

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http://doi.ieeecomputersociety.org/10.1109/DSD.2004.1333304

Euromicro Symposium on Digital System ...

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	Abdil Rashid Mohamed, Zebo Peng, Petru Eles, "A Heuristic for Wiring-Aware Built-In Self-Test Synthesis," Digital Systems Design, Euromicro Symposium on, pp. 408-415, Euromicro Symposium on Digital System Design (DSD'04), 2004.

	BibTex	x
	@article{ 10.1109/DSD.2004.1333304, author = {Abdil Rashid Mohamed and Zebo Peng and Petru Eles}, title = {A Heuristic for Wiring-Aware Built-In Self-Test Synthesis}, journal ={Digital Systems Design, Euromicro Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2203-3}, pages = {408-415}, doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2004.1333304}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Digital Systems Design, Euromicro Symposium on TI - A Heuristic for Wiring-Aware Built-In Self-Test Synthesis SN - 0-7695-2203-3 SP408 EP415 A1 - Abdil Rashid Mohamed, A1 - Zebo Peng, A1 - Petru Eles, PY - 2004 KW - BIST insertion KW - test synthesis KW - wiring area VL - 0 JA - Digital Systems Design, Euromicro Symposium on ER -

Abdil Rashid Mohamed, Link?ping University, Sweden

Zebo Peng, Link?ping University, Sweden

Petru Eles, Link?ping University, Sweden

This paper addresses the problem of BIST synthesis that takes into account wiring area. A technique for minimizing BIST hardware overhead is presented. The technique uses results of symbolic testability analysis to guarantee testability of all modules in the design. New behavioral-level BIST enhancement metrics are used to guide synthesis in such a way that the number of testability enhancements is minimized. The technique is not only fast but also adds low BIST overhead.

Index Terms:

BIST insertion, test synthesis, wiring area

Citation:

Abdil Rashid Mohamed, Zebo Peng, Petru Eles, "A Heuristic for Wiring-Aware Built-In Self-Test Synthesis," dsd, pp.408-415, Euromicro Symposium on Digital System Design (DSD'04), 2004

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