This paper presents an automated methodology for the design of low electromagnetic emissions digital circuits based on an optimized clock skew scheduling. The assumption that a unique clock signal must reach all memory elements of a circuit is common to all standard design flows for synchronous circuits. Unfortunately, the almost simultaneous switching of all gates in the circuit is responsible for very sharp and narrow peaks of current absorption from the power supply line. The consequent steepness of rising and falling edges of these current pulses will result in significant contributions on a very wide range of frequencies and therefore can be considered the main cause for both conducted and radiated emissions in integrated circuits. A fully automated design flow has been developed integrating new tools with standard tools and allowing the designer to desynchronize a synchronous circuit. Our tools are able to read the Standard Delay File of a circuit, to derive a set of relative timing constraints for the clock inputs of each memory element in the circuit and then to generate a partition of the circuit into a given number of clock domains. The methodology and the tools have been tested on a 16 bit microprocessor with 5 stages of pipeline showing a dramatic reduction of the current spectrum in the range of frequencies between 100MHz and 1GHz.