This paper presents an area efficient, low-power and robust ACS unit for Viterbi Decoder in two synchronous and asynchronous architectures. The asynchronous design is based upon Quasi Delay Insensitive (QDI) timing model which leads to a robust and low power purpose and synchronous architecture uses a hybrid CMOS-Pseudo NMOS technology to improve area and throughput factors. Some optimization techniques to reduce the power and area are applied to each design. The simulation results show the asynchronous design has the lowest power consumption with 6.65mW and hybrid CMOS has the lowest transistor counts with 759 in relative to other reported circuits.