Performance constraints play a key role in VLSI design. Performance constraints evaluation help in discovering requirements specification errors at an early stage in the design process when they are easy to fix. VSPEC is a requirements specification language for digital systems that contains a standard method for describing constraints. This paper presents a method of evaluating and verifying these constraints. Performance Description Language(PDL) is used for evaluation. The system is implemented within the ORBIT design environment.
Index Terms:
performance constraints evaluation, constraints verification
Citation:
Amitvikram Rajkhowa, Perry Alexander, "VSPEC Constraints Modeling and Evaluation," ecbs, pp.159, IEEE Conference and Workshop on Engineering of Computer-Based Systems, 1999