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Area-time performance of VLSI FIR filter architectures based on residue arithmetic
Budapest, HUNGARY September 01-September 04
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/EURMIC.1997.61737623rd EUROMICRO Conference '97 New Fro ...
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V. Paliouras, T. Stouraitis, "Area-time performance of VLSI FIR filter architectures based on residue arithmetic," EUROMICRO Conference, pp. 576, 23rd EUROMICRO Conference '97 New Frontiers of Information Technology, 1997.
 
 
BibTex
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@article{ 10.1109/EURMIC.1997.617376,
author = {V. Paliouras and T. Stouraitis},
title = {Area-time performance of VLSI FIR filter architectures based on residue arithmetic},
journal ={EUROMICRO Conference},
volume = {0},
year = {1997},
issn = {1089-6503},
pages = {576},
doi = {http://doi.ieeecomputersociety.org/10.1109/EURMIC.1997.617376},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - EUROMICRO Conference
TI - Area-time performance of VLSI FIR filter architectures based on residue arithmetic
SN - 1089-6503
SP
EP
A1 - V. Paliouras,
A1 - T. Stouraitis,
PY - 1997
KW - FIR filters; area-time performance optimization; VLSI FIR filter architectures; residue arithmetic; residue number system; FIR processors; performance models; moduli bases; binary-to-residue conversion complexity; residue-to-binary conversion complexity; Chinese remainder theorem; multiply-by-constant units; binary structures
VL - 0
JA - EUROMICRO Conference
ER -
 
V. Paliouras, Dept. of Electr. Eng. & Comput. Eng., Patras Univ., Greece
T. Stouraitis, Dept. of Electr. Eng. & Comput. Eng., Patras Univ., Greece
The area-time (A/spl middot/T) optimization of a particular class of residue number system (RNS)-based FIR processors is discussed in this paper. To facilitate the optimization procedure, a number of performance models are introduced. Furthermore, moduli bases are attained that lead to RNS FIR filter architectures of minimal A/spl middot/T/sup 2/ product. The A/spl middot/T/sup 2/ performance models include the binary-to-residue and residue-to-binary conversion complexity. In particular, efficient Chinese remainder theorem (CRT) architectures are derived, based on multiply-by-constant units (MCUs), which are systematically designed by an introduced methodology. The A/spl middot/T/sup 2/ performance of the derived residue FIR filter architectures is found to surpass equivalent binary structures under certain conditions.
Index Terms:
FIR filters; area-time performance optimization; VLSI FIR filter architectures; residue arithmetic; residue number system; FIR processors; performance models; moduli bases; binary-to-residue conversion complexity; residue-to-binary conversion complexity; Chinese remainder theorem; multiply-by-constant units; binary structures
Citation:
V. Paliouras, T. Stouraitis, "Area-time performance of VLSI FIR filter architectures based on residue arithmetic," euromicro, pp.576, 23rd EUROMICRO Conference '97 New Frontiers of Information Technology, 1997
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