This paper discusses high-level synthesis problems and solutions specific for low power synthesis. It presents a method for power consumption minimization by switched capacitance reduction during operation scheduling and resource binding. This process uses switching activity data obtained from simulation of the design at the register transfer level. The novelty of our approach is the use of constraint logic programming which enables minimization of the switching activity while performing both scheduling and binding in one synthesis step. The experimental results confirm the importance and the feasibility of the described method.