This work presents a new hardware cache management approach for improving the cache hit ratio and reducing the bus traffic. Increasing the L1 cache hit ratio is a crucial aspect of obtaining good performance with the current processors. The proposed approach also increases the overall (L1 plus L2) cache hit ratio, especially in multiprocessor systems, where the bus latencies are low.This work focuses in multiprocessor systems where a forth kind of miss (the coherence miss) and the bus utilization problem appear; however, the model can also be applied to uniprocessor systems. Our organization increases the overall cache hit ratio and thus reduces the bus utilization.The proposed model introduces two independent L1 caches with different organizations placed in parallel. Each cache block has attached to it a small counter for storing the reuse related information. The proposed microarchitecture not only reduces the bus traffic and speeds up better than the conventional organization, but it also saves die area. The performance (versus conventional cache organizations) increases as the number of processors increases.