Technology mapping for Multiplexor (MUX) based Field Programmable Gate Arrays (FPGAs) has widely been considered. Here, a new algorithm is proposed that applies techniques from logic synthesis during mapping. This considers the target technology considered in the minimization process. Binary Decision Diagrams (BDDs) are used as an underlying data structure due to the close relation between BDDs and MUX netlists. The algorithm uses local do not cares obtained by a greedy algorithm. Computing signatures speeds up the mapping. The user can specify a trade-off quality versus run-time by setting different parameters. Experimental results comparing the approach to the best-known results show improvements of more than 30% for area and 40% for delay for many instances.