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Testability of Circuits Derived from Lattice Diagrams
Maastricht, The Netherlands September 05-September 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/EURMIC.2000.874632Proceedings of The 26th EUROMICRO Con ...
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Rolf Drechsler, Wolfgang Günther, Bernd Becker, "Testability of Circuits Derived from Lattice Diagrams," EUROMICRO Conference, vol. 1, pp. 1188, Proceedings of The 26th EUROMICRO Conference (EUROMICRO'00) Volume I-Volume 1, 2000.
 
 
BibTex
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@article{ 10.1109/EURMIC.2000.874632,
author = {Rolf Drechsler and Wolfgang Günther and Bernd Becker},
title = {Testability of Circuits Derived from Lattice Diagrams},
journal ={EUROMICRO Conference},
volume = {1},
year = {2000},
isbn = {0-7695-0780-8},
pages = {1188},
doi = {http://doi.ieeecomputersociety.org/10.1109/EURMIC.2000.874632},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - EUROMICRO Conference
TI - Testability of Circuits Derived from Lattice Diagrams
SN - 0-7695-0780-8
SP
EP
A1 - Rolf Drechsler,
A1 - Wolfgang Günther,
A1 - Bernd Becker,
PY - 2000
VL - 1
JA - EUROMICRO Conference
ER -
 
Rolf Drechsler, Albert-Ludwigs-University
Wolfgang Günther, Albert-Ludwigs-University
Bernd Becker, Albert-Ludwigs-University
In this paper the testability of circuits derived from BDDs representing totally symmetric functions is analyzed. A test pattern generation technique is presented that has runtime linear in the size of the BDD. The result is directly applicable to circuits derived from lattice diagrams, a new design style that combines the synthesis and the layout step. Experimental results show that complete test generation for functions with more than 500 variables can be done in less than one CPU second.
Citation:
Rolf Drechsler, Wolfgang Günther, Bernd Becker, "Testability of Circuits Derived from Lattice Diagrams," euromicro, vol. 1, pp.1188, Proceedings of The 26th EUROMICRO Conference (EUROMICRO'00) Volume I-Volume 1, 2000
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