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Achieving Minimal and Deterministic Interrupt Execution in Stack-Based Processor Architectures
Maastricht, The Netherlands September 05-September 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/EURMIC.2000.874655Proceedings of The 26th EUROMICRO Con ...
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Chris Bailey, University of York
Whilst stack-processors have enjoyed a renewed interest since the emergence of JAVA technology, stack-processors suffer from a major bottleneck - the constant movement of stack content to and from memory (stack-spilling). With 70% to 80% of instructions generating a stack-spill (see introduction), performance can be significantly diminished in the absence of a cache. In order to overcome this problem, very small and simple 'stack buffers' may be used to eliminate virtually all stack-spills for very little cost in silicon. Unfortunately, this introduces an indeterministic element of system behaviour, especially with respect to interrupts. In this paper the positive benefits of stack-buffers are assessed, as well as the penalties introduced in terms of interrupt performance in a stack-based architecture. Then a new mechanism for managing interrupt conditions with stack buffers, ?stack buffer windowing? is presented. This is shown to deliver deterministic interrupt response whilst maintaining the reduced stack-spill overheads associated with normal buffering schemes.
Citation:
Chris Bailey, "Achieving Minimal and Deterministic Interrupt Execution in Stack-Based Processor Architectures," euromicro, vol. 1, pp.1368, Proceedings of The 26th EUROMICRO Conference (EUROMICRO'00) Volume I-Volume 1, 2000
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